1. Field of the Invention
The present invention relates to ultra high voltage semiconductor devices and, more particularly, to an ultra high voltage MOS transistor capable of alleviating or eliminating high vertical electric field effect caused by the gate edge, and being compatible with low-voltage device.
2. Description of the Prior Art
High voltage or ultra high voltage metal-oxide-semiconductor (MOS) transistor devices are known in the art. Ordinarily, an ultra high voltage MOS transistor device can sustain a drain voltage of several hundreds or thousands volts. FIG. 1 schematically illustrates a cross-sectional view of a prior art ultra high voltage NMOS transistor device. The prior art ultra high voltage NMOS transistor device 1 is fabricated on an active area of a semiconductor substrate 10 such as a P type silicon substrate. The active area is defined with a peripheral field oxide layer 44. The ultra high voltage NMOS transistor device 1 comprises a heavily N doped source 14, a gate 50 and a heavily N doped drain 24. The heavily N doped source 14 borders upon a heavily P doped region 16, both of which are formed within a P well 12. The distance between the drain 24 and the source 14 may be few micrometers. As shown in FIG. 1, the heavily N doped drain 24 is formed within a grade N well 22 that is formed within a deep N well 30.
A gate oxide film 46 is formed on the heavily N doped source 14. The gate 50 is formed on the gate oxide film 46 and laterally extends over a field oxide layer 42 that is formed on the semiconductor substrate 10 between the source 14 and drain 24. A plurality of floating field plates 52 are disposed on the field oxide layer 42 between the gate 50 and the drain 24. These electrically floating field plates 52 are used to disturb lateral electric field when this ultra high voltage MOS device is in operation. Like the peripheral field oxide layer 44, the field oxide layer 42 is formed using conventional local oxidation of silicon (LOCOS) technique. To prevent breakdown of the MOS device operated at a high voltage ranging between hundreds and thousands volts, a very thick field oxide layer 42 having a thickness t of at least 10,000 angstroms is required. It is evident that when the thickness t of the field oxide layer 42 is greater than 10,000 angstroms, the high vertical electric field caused by the sharp lower gate edge 70 can be significantly reduced.
However, it is problematic to form such thick field oxide layer 42 because it takes extra time. The wafers will have to stay in the furnace longer, and this means reduced throughput. Further, a thicker field oxide layer also leads to severer bird's beak effect on the low-voltage device area, and thus consuming more valuable chip surface area. Therefore, there is a need in this industry to provide an improved ultra high voltage MOS transistor device that is compatible with low voltage device having field oxide thickness of about 5,000-6,000 angstroms and, on the other hand, the ultra high voltage MOS transistor device is capable of solving high vertical electric field caused by the gate edge.